Itanium: Difference between revisions

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[[File:Intel Itanium Logo.png|thumb|Explicitly parallel instruction computing]]
Itanium, also known as IA-64 and IPF (Itanium Processor Family), is a RISC-like CPU architecture developed by HPE and Intel in the 1990s to serve as a high end, 64-bit, RISC processor architecture to replace HP's PA-RISC. Incidentally, SGI also adopted it to replace [[MIPS]] due to being unable to continue MIPS development due to early 2000s financial difficulties.  
Itanium, also known as IA-64 and IPF (Itanium Processor Family), is a RISC-like CPU architecture developed by HPE and Intel in the 1990s to serve as a high end, 64-bit, RISC processor architecture to replace HP's PA-RISC. Incidentally, SGI also adopted it to replace [[MIPS]] due to being unable to continue MIPS development due to early 2000s financial difficulties.  


=== History of Itanium ===
== History of Itanium ==
In 1989 the Fort Collins Design Center, a part of Hewlett Packard, but now a part of Intel, began work on a new RISC architecture to exceed the performance of current RISC iterations. Intel joined the alliance in 1994 and quickly became the face of Itanium.  
In 1989 the Fort Collins Design Center, a part of Hewlett Packard, but now a part of Intel, began work on a new RISC architecture to exceed the performance of current RISC iterations. Intel joined the alliance in 1994 and quickly became the face of Itanium.  


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By 2005, IBM, Sun, Dell and many others had mostly evacuated the Itanium alliance, leaving HP and several Japanese companies (e.g. Hitachi) as Intel's primary customer. SGI shipped Itanium, but not in sufficient volume, and by 2008 SGI declared bankruptcy.  
By 2005, IBM, Sun, Dell and many others had mostly evacuated the Itanium alliance, leaving HP and several Japanese companies (e.g. Hitachi) as Intel's primary customer. SGI shipped Itanium, but not in sufficient volume, and by 2008 SGI declared bankruptcy.  


=== Design ===
In 2017, a higher stepping of Poulson, called Kittson, shipped and was the last Itanium processor type. All units were shipped by mid-2019. 
 
== Design ==
Itanium uses the EPIC (Explicitly Parallel Instruction Computing), but internally it resembles the Berkeley RISC design, with register windowing, in-order opcode loading, mostly fixed length instructions, etc. It differs from traditional RISC in using VLIW-like instruction bundling to enable parallel execution. It additionally had 64-bit SIMD instructions, similar to MMX.
Itanium uses the EPIC (Explicitly Parallel Instruction Computing), but internally it resembles the Berkeley RISC design, with register windowing, in-order opcode loading, mostly fixed length instructions, etc. It differs from traditional RISC in using VLIW-like instruction bundling to enable parallel execution. It additionally had 64-bit SIMD instructions, similar to MMX.


== Performance ==
Itanium was smashed by public consumer media due to dishonest benchmarking (x86 emulation mode used for benchmarking, and other dishonest claims) and seen as a poor replacement for x86, which it was never designed to do. It often led during the mid-2000s on [https://www.spec.org/cpu2006/results/res2009q2/cpu2006-20090522-07485.html floating point and integer workloads] and was never intended as a general purpose CPU. Itanium's performance is often tied to the compiler used, with Open64 and GCC doing quite poorly compared to HP's aCC and Intel's C++ compiler.
== In SGIs ==
On the collector market, the Prism is often considered desirable, but all other SGI Itanium systems have never had the same cult following. This is due to a combination of factors:
* IRIX users do not find GNU/Linux particularly enticing.
* The systems only run Windows for Itanium and GNU/Linux itanium distributions.
As a result, most Altices can be had at bargain bin prices.
== Market Performance ==
Itanium shipped more than 4 billion units during its lifetime, the lion's share under HPE, with the remainder primarily under the Japanese market. By the time of Poulson and Kittson, however, it had very few new customers.
[[Category:Stubs]]
[[Category:Stubs]]
[[Category:Processors]]
[[Category:Processors]]

Latest revision as of 19:53, 23 February 2025

Explicitly parallel instruction computing

Itanium, also known as IA-64 and IPF (Itanium Processor Family), is a RISC-like CPU architecture developed by HPE and Intel in the 1990s to serve as a high end, 64-bit, RISC processor architecture to replace HP's PA-RISC. Incidentally, SGI also adopted it to replace MIPS due to being unable to continue MIPS development due to early 2000s financial difficulties.

History of Itanium

In 1989 the Fort Collins Design Center, a part of Hewlett Packard, but now a part of Intel, began work on a new RISC architecture to exceed the performance of current RISC iterations. Intel joined the alliance in 1994 and quickly became the face of Itanium.

Due to delays and development hell, the 1997-1998 launch window was missed and Merced, the initial Itanium design, only began shipping volume around 2001. At that time, Merced was neither competitive or impressive. This, combined with continued delays of Itanium 2, negative press from consumer publications misunderstanding Itanium's purpose (It was never designed to replace x86) and mismanagement led many partners to evacuate the Itanium alliance.

By 2005, IBM, Sun, Dell and many others had mostly evacuated the Itanium alliance, leaving HP and several Japanese companies (e.g. Hitachi) as Intel's primary customer. SGI shipped Itanium, but not in sufficient volume, and by 2008 SGI declared bankruptcy.

In 2017, a higher stepping of Poulson, called Kittson, shipped and was the last Itanium processor type. All units were shipped by mid-2019.

Design

Itanium uses the EPIC (Explicitly Parallel Instruction Computing), but internally it resembles the Berkeley RISC design, with register windowing, in-order opcode loading, mostly fixed length instructions, etc. It differs from traditional RISC in using VLIW-like instruction bundling to enable parallel execution. It additionally had 64-bit SIMD instructions, similar to MMX.

Performance

Itanium was smashed by public consumer media due to dishonest benchmarking (x86 emulation mode used for benchmarking, and other dishonest claims) and seen as a poor replacement for x86, which it was never designed to do. It often led during the mid-2000s on floating point and integer workloads and was never intended as a general purpose CPU. Itanium's performance is often tied to the compiler used, with Open64 and GCC doing quite poorly compared to HP's aCC and Intel's C++ compiler.

In SGIs

On the collector market, the Prism is often considered desirable, but all other SGI Itanium systems have never had the same cult following. This is due to a combination of factors:

  • IRIX users do not find GNU/Linux particularly enticing.
  • The systems only run Windows for Itanium and GNU/Linux itanium distributions.

As a result, most Altices can be had at bargain bin prices.

Market Performance

Itanium shipped more than 4 billion units during its lifetime, the lion's share under HPE, with the remainder primarily under the Japanese market. By the time of Poulson and Kittson, however, it had very few new customers.