Itanium
Itanium, also known as IA-64 and IPF (Itanium Processor Family), is a RISC-like CPU architecture developed by HPE and Intel in the 1990s to serve as a high end, 64-bit, RISC processor architecture to replace HP's PA-RISC. Incidentally, SGI also adopted it to replace MIPS due to being unable to continue MIPS development due to early 2000s financial difficulties.
History of Itanium
In 1989 the Fort Collins Design Center, a part of Hewlett Packard, but now a part of Intel, began work on a new RISC architecture to exceed the performance of current RISC iterations. Intel joined the alliance in 1994 and quickly became the face of Itanium.
Due to delays and development hell, the 1997-1998 launch window was missed and Merced, the initial Itanium design, only began shipping volume around 2001. At that time, Merced was neither competitive or impressive. This, combined with continued delays of Itanium 2, negative press from consumer publications misunderstanding Itanium's purpose (It was never designed to replace x86) and mismanagement led many partners to evacuate the Itanium alliance.
By 2005, IBM, Sun, Dell and many others had mostly evacuated the Itanium alliance, leaving HP and several Japanese companies (e.g. Hitachi) as Intel's primary customer. SGI shipped Itanium, but not in sufficient volume, and by 2008 SGI declared bankruptcy.
Design
Itanium uses the EPIC (Explicitly Parallel Instruction Computing), but internally it resembles the Berkeley RISC design, with register windowing, in-order opcode loading, mostly fixed length instructions, etc. It differs from traditional RISC in using VLIW-like instruction bundling to enable parallel execution. It additionally had 64-bit SIMD instructions, similar to MMX.
