Odyssey Pixel Clock Bug Workaround

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Revision as of 17:56, 10 February 2025 by Raion (talk | contribs) (Created page with "The first-generation Odyssey boards used in the Octane (V6 and V8) have a known pixel clock bug. The bug manifests in 109-193MHz pixel clocks (display frequency, in simple terms, not to be confused with the refresh rate). To work around these limitations, a few methods have been devised: ==== Simplest: Use a different resolution ==== At risk of stating the obvious, the simplest way is to use a predefined resolution that is not subject to the hardware limitation. An absu...")
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The first-generation Odyssey boards used in the Octane (V6 and V8) have a known pixel clock bug. The bug manifests in 109-193MHz pixel clocks (display frequency, in simple terms, not to be confused with the refresh rate). To work around these limitations, a few methods have been devised:

Simplest: Use a different resolution

At risk of stating the obvious, the simplest way is to use a predefined resolution that is not subject to the hardware limitation. An absurdly low resolution will undercut the pixel clock bug.

Easiest Real Solution: Change the refresh rate

Using the VFC compiler: http://tech-pubs.net/SGI_misc/vfc_guide_o2.html

One can make a custom VFC file and put it into 

 /usr/gfx/ucode/ODSY/vof/

and then select the appropriate resolution and refresh rate.

More Complicated: Change other parameters

There's no tried and true method here, but blanking intervals can be changed as well as other functions. The guide above is among the best in terms of quality and completeness.

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