MIPS

MIPS, standing for "Microprocessor without Interlocked Pipelined Stages" is a RISC CPU architecture developed firstly by MIPS Computer Systems, then later Silicon Graphics, and now by MIPS Technologies. MIPS is derived from the Stanford RISC project and mostly conforms to the basic design conventions of that standard.

History

The first version of the MIPS CPU was the R2000 microprocessor, released in 1985. MIPS Computer Systems used the R2000 as the main CPU for their systems running RISC/OS.

ISA

MIPS began in 1985 with the MIPS I standard, then later MIPS II, III and IV were released as iterations upon the same architecture. MIPS is a load/store architecture (also known as a register-register architecture); except for the load/store instructions used to access memory, all instructions operate on the registers.

MIPS I

MIPS I has thirty-two 32-bit general-purpose registers. Register $0 is hardwired to zero and writes to it are discarded. Register $31 is the link register. For integer multiplication and division instructions, which run asynchronously from other instructions, a pair of 32-bit registers, HI and LO, are provided. There is a small set of instructions for copying data between the general-purpose registers and the HI/LO registers.

The program counter has 32 bits. The two low-order bits always contain zero since MIPS I instructions are 32 bits long and are aligned to their natural word boundaries.

Instruction formats

Instructions are divided into three types: R (register), I (immediate), and J (jump). Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target.

The following are the three formats used for the core instruction set:

Type	-31-                                 format (bits)                                 -0-
R	opcode (6)	rs (5)	rt (5)	rd (5)	shamt (5)	funct (6)
I	opcode (6)	rs (5)	rt (5)	immediate (16)
J	opcode (6)	address (26)